The present invention relates to integrated circuits and their design.
In recent years, the design of integrated circuit processors has shifted from standalone proprietary designs to designs which support greater networking capability and interoperability with competing designs and legacy platforms. This coincides with a realignment of the computing world with network server computers, replacing the traditionally dominant standalone PCs.
Accordingly, it is no longer enough to provide a processor having the highest standalone performance. The processor must be adept at handling the computing job at hand, which means efficiently responding to processing calls. A processor design that supports calls arriving from a variety of differently designed processors of different vendors would be superior, as it would offer a greater degree of interoperability. However, among such designs, higher performance would be achieved when the processors in a network, be they large or small, server or client, share common design features, as described in commonly owned U.S. patent application Ser. No. 09/815,554, filed Mar. 22, 2001, which is hereby incorporated by reference herein. Such common designs may utilize a common architecture having a common instruction set architecture (ISA) or subportions thereof, and a common design for data paths and addressing. Such common designs may also support high execution rates for jobs such as the serving and/or processing of graphics data. Such designs would support interoperability while promoting the high performance benefits of a shared design.
In designing processors for such purpose, an efficient processor organization and design method are needed. A relatively short design cycle should be realized, regardless of the size of the processor, or the computing job that it is designed to support. The processor design should be capable of being changed while continuing to implement a common instruction set architecture. Moreover, the processor design should be capable of being changed close to the time that it is released to manufacturing on an integrated circuit (IC) without requiring large-scale redesign of the processor and without requiring large-scale redesign of microcode and hardware to implement the instruction set on the changed processor.
FIG. 1 is a flow diagram illustrating a processor implementation method according to the prior art. As shown in FIG. 1, an initial step S01 in the design of a processor includes designing a new instruction set architecture and/or extensions to an existing instruction set architecture, both of which are collectively referred to herein as “ISA”. The instruction set architecture is a collection of machine-language instructions that the processor is required to recognize and execute whenever such instructions are presented to the processor. An ISA typically includes instructions for storing and retrieving data, storing and retrieving instructions, and for mathematically, logically or otherwise manipulating operands and other instructions held in one or more registers of the processor. The ISA is typically detailed to a point in which only a particular processor or class or processors is capable of executing the instructions thereof. Details of the ISA include the data width of bits to be retrieved from storage per access, and types of fetch commands by which data bits can be accessed directly. In addition, support for movement of data between registers of the processor and different levels of storage, e.g. different levels of cache, are typically specific to a processor design or class of processors. As a further example, while processors having different organizations are capable of executing floating point operations, only processors belonging to a particular class of processors are capable of executing floating point operations in which the mantissa has a length of 32 bits, the exponent has length of 16 bits, and the two's complement is used to indicate the sign of a number.
In this method according to the prior art, after the ISA is designed, the processor is then custom designed (step S03) to have a fixed functional organization which supports the design of the ISA. The ISA including any extensions thereof is typically designed to such detail that it can only be implemented by processor hardware having a very specific functional organization. As discussed above, as an example, the bit width for transferring data to and from registers of the processor, and the bit width of operands capable of manipulation by the processor are typically fixed by the instructions included within the ISA. Accordingly, the design of the processor reduces to a process of designing fixed hardware and/or microcode support for the instructions of the ISA.
Thereafter, at step S05, issue logic and microcode are custom-designed to implement the instructions on the processor hardware designed therefor. Issue logic is used to convert an instruction having a symbol of limited bitwidth (e.g. 32 bits of character data) recognizable by the processor and by a human or machine-based programmer (compiler) to a set of electrical signals which turn on and turn off various elements of the processor hardware, as needed to execute the instruction. Such symbol to signal conversion is typically performed either by hardware or in firmware by look-up of stored data representing such signals. For example, a microcoded instruction is implemented by data stored in a control store which represents such signals. The stored data is fetched, as from a control store, upon recognition of the symbol for a particular instruction and is then used to provide the signals which execute the instruction on the processor. According to the prior art method, the design of the issue logic and the microcode are generally performed subsequent to the design of the hardware because they are dependent upon choices made during the hardware design.
However, in the design method according to the prior art, a problem exists when seeking to modify the design of the processor. At step S03, the processor is designed having a fixed functional organization to support the ISA. The issue logic and microcode are then custom-designed to implement the ISA on the custom-designed processor. However, because of their custom-design, when the design of the processor is modified, the issue logic and microcode previously designed therefor might no longer work in the modified processor design. Accordingly, whenever a decision is made to modify the design of the processor (S06), the process flow returns to the step of the processor design at S03, reflecting that a change in the processor design can require changes in the design of issue logic and microcode to implement the ISA on the modified processor design.
In addition to the above considerations, two existing methodologies are provided by the prior art for designing processors according to step S03 of the above-described method: synthetic design, and custom design. These design methodologies find particular application to the design of processor “cores”, i.e., processor elements of integrated circuits that have additional function. An integrated circuit classified as a system-on-a-chip (“SOC”) has a processor core.
In the synthetic design approach, as illustrated in FIG. 2, a library of reusable component blocks is developed a priori, as shown at S10, the library being available for designing many varieties of circuits for use in systems having a range of clock speeds and purposes. The reusable component blocks are defined by relatively high-level language, for example, a register transport level (“RTL”) description. The designer then assembles the processor design by specifying the component blocks for use therein, as shown at S12. A compiler synthesizes a circuit layout from the component blocks specified in the RTL description. Synthetic design provides flexibility to modify essential features of the processor during the design cycle such as the instruction set, the width of pipelines, and the size of the cache. Such modifications are made by specifying a different set of reusable component blocks in the RTL description, as shown at S14. Synthetic design also allows designs to be created and ready for testing (at a pre-hardware stage) within a relatively short design cycle.
Custom design, on the other hand, is painstaking, requiring a relatively long design cycle. As illustrated in FIG. 3, in a full custom design of a processor, the elements of the processor are designed from the bottom level up, including all functional blocks, as shown at S20. Circuits are handcrafted to specific performance criteria, e.g., to support a minimum clock frequency, to consume less than a certain limit of power, or to occupy less than a certain limit of integrated circuit area. The layout and wiring between functional blocks are also carefully designed to meet the performance criteria, as shown at S22. Because of the greater attention given to each element of the design and the specific emphasis on meeting performance criteria, up to four times greater performance can be achieved when custom designing a processor versus creating the design synthetically. On the other hand, modifying the custom design poses difficulties, because it requires re-designing the processor again from the bottom level up, as shown at S24.
Moreover, as indicated above with reference to FIG. 1, a modification to the processor design forces reevaluation and redesign of the issue logic and microcode to implement the ISA on the modified processor design.
Accordingly, it would be desirable to provide a processor having a modular functional organization having capabilities determined according to a number of modular elements provided in the processor.
It would further be desirable to provide a method of designing a processor which does not require redesign of the issue logic and microcode when a change is made in the processor design, for example, a change in the number of functional units of the processor.